Description
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
Affected products
Version statuses are supplied by the assigning organization. Consult the original record for detailed ranges and platform conditions.
n/a Intel(R) Processors
Default version status: unaffected
See referencesaffected
References
- https://intel.com/content/www/us/en/security-center/advisory/intel-sa-01153.html ↗
- http://xenbits.xen.org/xsa/advisory-469.html ↗
- http://www.openwall.com/lists/oss-security/2025/05/12/5 ↗
- https://lists.debian.org/debian-lts-announce/2025/10/msg00007.html ↗
- https://lists.debian.org/debian-lts-announce/2025/08/msg00010.html ↗
- https://lists.debian.org/debian-lts-announce/2025/05/msg00021.html ↗
- https://cert-portal.siemens.com/productcert/html/ssa-019113.html ↗
- https://cert-portal.siemens.com/productcert/html/ssa-457936.html ↗