Description
Due to a code bug in Secure_TSC, SEV firmware may allow an attacker with high privileges to cause a guest to observe an incorrect TSC when Secure TSC is enabled potentially resulting in a loss of guest integrity.
Affected products
Version statuses are supplied by the assigning organization. Consult the original record for detailed ranges and platform conditions.
AMD 3rd Gen AMD EPYC™ Processors
Default version status: affected
variousaffected
AMD 4th Gen AMD EPYC™ Processors
Default version status: affected
variousaffected